ignore returned value procedure/function VHDL -

i have several functions , procedures in vhdl package. wanted ask if there way of ignore out items of these. know open keyword port maps. using dummy signals assigned procedure out. might more efficient way this.

¿is there such thing vhdl? if set out signals open following error: "formal e5 of mode out must have associated actual"

thanks in advance, antonio

edited: code

procedure reg2ind  (signal reg : in std_logic_vector(15 downto 0);   signal e1,e2,e3,e4,e5,e6,e7,e8 : out std_logic;   signal e9,e10,e11,e12,e13,e14,e15,e16 : out std_logic)  begin   e1 <= reg(0);   e2 <= reg(1);         e3 <= reg(2);   e4 <= reg(3);   e5 <= reg(4);   e6 <= reg(5);   e7 <= reg(6);   e8 <= reg(7);   e9 <= reg(8);   e10 <= reg(9);   e11 <= reg(10);   e12 <= reg(11);   e13 <= reg(12);   e14 <= reg(13);   e15 <= reg(14);   e16 <= reg(15); end reg2ind; 

when use it:

reg2ind(val183,ord_p.err.err_17,ord_p.err.err_18, ord_p.err.err_19,ord_p.err.err_20,open,open,open,open,open,open, open,open,open,open, open,open); 

the lack of mcve isn't critical understanding analysis error.

see ieee std 107-2008, 10.7 procedure call statement, para 4:

for each formal parameter of procedure, procedure call shall specify 1 corresponding actual parameter. actual parameter specified either explicitly, association element (other actual open) in association list or, in absence of such association element, default expression (see 6.5.2).

see 4.2 subprogram declarations, 4.2.2.3 signal parameters para 1:

for formal parameter of class signal, references signal, driver of signal, or both, passed subprogram call.

and para 6:

if actual signal associated signal parameter of mode, actual shall denoted static signal name. error if conversion function or type conversion appears in either formal part or actual part of association element associates actual signal formal signal parameter.

also see 14.6 dynamic elaboration, para 2, b) (in part):

execution of subprogram call involves elaboration of parameter association list. ...

dynamic elaboration incompatible open removes drivers other calls same procedure might require.

so rule shown in 4.2 subprogram declarations, 4.2.2.3 signal parameters paragraph 6 requires actual static signal name.

this particular example of procedure uninteresting, assigning elements of array input signal outputs.

an mcve:

library ieee; use ieee.std_logic_1164.all;  entity foo end entity;  architecture fum of foo        procedure reg2ind      (signal reg : in std_logic_vector(15 downto 0);       signal e1,e2,e3,e4,e5,e6,e7,e8 : out std_logic;       signal e9,e10,e11,e12,e13,e14,e15,e16 : out std_logic)      begin       e1 <= reg(0);       e2 <= reg(1);             e3 <= reg(2);       e4 <= reg(3);       e5 <= reg(4);       e6 <= reg(5);       e7 <= reg(6);       e8 <= reg(7);       e9 <= reg(8);       e10 <= reg(9);       e11 <= reg(10);       e12 <= reg(11);       e13 <= reg(12);       e14 <= reg(13);       e15 <= reg(14);       e16 <= reg(15);     end procedure reg2ind;      signal val183:  std_logic_vector (15 downto 0);     type err_record         record             err_17: std_logic;             err_18: std_logic;             err_19: std_logic;             err_20: std_logic;         end record;     type some_record          record         err: err_record;         end record;      signal ord_p: some_record;      signal open5, open6, open7,            open8, open9, open10,            open11, open12, open13,            open14, open15, open16:      std_logic; begin      reg2ind(val183,ord_p.err.err_17,ord_p.err.err_18,     ord_p.err.err_19,ord_p.err.err_20,open5,open6,open7,open8,open5,open6,     open7,open8,open9,open10, open11,open12);  -- dummy outputs      -- reg2ind(val183,ord_p.err.err_17,ord_p.err.err_18,     -- ord_p.err.err_19,ord_p.err.err_20,open,open,open,open,open,open,     -- open,open,open,open, open,open);  -- presented  fails   end architecture; 

the interested reader can explore limitations of using signal based parameters.

the simplest solution might use aggregate assignment target elements re-arranged match actual's ordering instead of procedure call:

    (ord_p.err.err_20, ord_p.err.err_19, ord_p.err.err_18, ord_p.err.err_17) <=         val183(3 downto 0); 

re-arranging target allows right hand side slice name instead of aggregate required qualified expression. less textual complexity procedure call.

any impetus hiding detail using procedure call accompanied providing procedure fewer parameters.

function calls expressions , it's not semantically possible ignore result value. enclose statement containing function call or procedure call statement in conditionally executed statement (e.g. if statement, case statement).