fpga - How to see content of look up table -

imagine have simple code fpga, want know if there way watch content of specific lookup table after synthesis, data written in sram

module test8(a,b,c      );     input ;      input b ;     output c;      assign c = a&b;  endmodule 

simple , gate

the possibility depends on fpga vendors tool.

some tools has gui floor-plan view used luts can found, , these luts can have associated code attached memory contents of lut. in altera queatus chip planner may like:

another option generate netlist of complete design, writable fpga tool, , netlist contain luts code lut contents. in altera quartus generated verilog netlist may like:

... // location: labcell_x10_y34_n0 cyclonev_lcell_comb \c~0 ( // equation(s): // \c~0_combout  = ( \a~input0  & ( \b~input0  ) )      .dataa(gnd),     .datab(gnd),     .datac(!\b~input0 ),     .datad(gnd),     .datae(gnd),     .dataf(!\a~input0 ),     .datag(gnd),     .cin(gnd),     .sharein(gnd),     .combout(\c~0_combout ),     .sumout(),     .cout(),     .shareout()); // synopsys translate_off defparam \c~0 .extended_lut = "off"; defparam \c~0 .lut_mask = 64'h000000000f0f0f0f; defparam \c~0 .shared_arith = "off"; // synopsys translate_on ... 

note gui view shows , gate not implemented using single simple lut, since tools has freedom implement seems fit, long timing , other requirements observed.

but in end, specific implementation , considerations lut coding ignored designer... except in special debugging cases.