Read textfile in VHDL testbench -

i have file source.txt, looks this:

00660066006700670067006800680069006b006d006e 00660066006700670067006800680069006b006d006e 00660066006700670067006800680069006b006d006e 00660066006700670067006800680069006b006d006e 00660066006700670067006800680069006b006d006e 0065006500660067006700690069006a006b006c006e 00650065006600670067006700680069006a006c006d 00650065006600670067006600660068006a006b006d 006500650066006700670065006600670069006b006d 00650065006600670067006600670068006a006c006d 0065006500660067006700690069006a006b006c006e * 

after each line there hidden newline character '\n'. asterix '*' visible end-of-file character.

how write testbench in vhdl following:

• read file
• store 1 line in vector
• write vector in new target.txt

using vhdl-2008, , showing std_logic_vector underway, code can be:

library ieee; use ieee.std_logic_1164.all; use std.textio.all;  entity tb end entity;  architecture syn of tb begin   process     variable line_v : line;     file read_file : text;     file write_file : text;     variable slv_v : std_logic_vector(44 * 4 - 1 downto 0);   begin     file_open(read_file, "source.txt", read_mode);     file_open(write_file, "target.txt", write_mode);     while not endfile(read_file) loop       readline(read_file, line_v);       hread(line_v, slv_v);       report "slv_v: " & to_hstring(slv_v);       hwrite(line_v, slv_v);       writeline(write_file, line_v);     end loop;     file_close(read_file);     file_close(write_file);     wait;   end process; end architecture;